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CS5378 Datasheet

  • CS5378

  • Low-power Single-channel Decimation Filter

  • 1532.00KB

  • 87页

  • CIRRUS

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CS5378
Low-power Single-channel Decimation Filter
Features
Single-channel Digital Decimation Filter
Multiple On-chip FIR and IIR Coefficient Sets
Programmable Coefficients for Custom Filters
Synchronous Operation
Description
The CS5378 is a multi-function digital filter utilizing a low-
power signal processing architecture to achieve efficient
filtering for a delta-sigma-type modulator. By combining
the CS5378 with a CS3301/02 differential amplifier, a
CS5371 modulator, and a CS4373 test DAC, a synchro-
nous high-resolution measurement system can be
designed quickly and easily.
Digital filter coefficients for the CS5378 FIR and IIR filters
are included on-chip for a simple setup, or they can be
programmed for custom applications. Selectable digital
filter decimation ratios produce output word rates from
4000 SPS to 1 SPS, resulting in measurement band-
widths ranging from 1600 Hz down to 400 mHz when
using the on-chip coefficient sets.
The CS5378 includes integrated peripherals to simplify
system design: a low-jitter PLL for standard clock or
manchester inputs, offset and gain corrections, a test
DAC bit stream generator, a time break controller, and
eight general-purpose I/O pins.
Integrated PLL for Clock Generation
1.024 MHz, 2.048 MHz, or 4.096 MHz Input
Standard Clock or Manchester Input
Selectable Output Word Rate
4000, 2000, 1000, 500, 333, 250 SPS
200, 125, 100, 50, 40, 25, 20, 10, 5, 1 SPS
Digital Gain and Offset Corrections
Test DAC Bit-stream Generator
Sine Wave or Impulse Output Mode
Time Break Controller, General-purpose I/O
Microcontroller or EEPROM Configuration
Small-footprint, 28-pin SSOP Package
Low Power Consumption
16 mW at 500 SPS OWR
Flexible Power Supplies
I/O Interface and PLL: 3.3 V or 5.0 V
Digital Logic Core: 2.5 V, 3.3 V or 5.0 V
I
ORDERING INFORMATION
See
page 86.
VDDCORE
SS:EECS
VDDPAD
VDDPLL
DRDY
MISO
MOSI
SCK
PLL, Clock Generation
Serial Interface
Reset, Synchronization
CLK
MCLK
RESET
SYNC
MSYNC
TIMEB
Time Break Controller
Decimation and
Filtering Engine
Test Bit Stream
Controller
TBSDATA
GPIO7:BOOT
GPIO6:PLL2
GPIO5:PLL1
GPIO4:PLL0
GPIO3
GPIO2
GPIO1
GPIO0
Modulator Data Interface
GPIO
General Purpose I/O
MDATA
MFLAG
GNDPAD
//www.cirrus.com
Copyright
Cirrus Logic, Inc. 2005
(All Rights Reserved)
GNDCORE
GNDPLL
OCT 鈥?5
DS639F1

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