鈩?/div>
(a)
* Capacitive Load consists of all com-
ponents of the test environment.
ALL INPUT PULSES
3.3V
90%
GND
Rise time > 1V/ns
10%
90%
10%
Fall time:
> 1V/ns
(c)
AC Switching Characteristics
Over the Operating Range
Parameter
Read Cycle
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
[8, 9]
t
WC
t
SCE
Write Cycle Time
CE
1
LOW/CE
2
HIGH to Write End
V
CC
(typical) to the first access
[5]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW / CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
[6]
CE
1
LOW/CE
2
HIGH to Low-Z
[6]
CE
1
HIGH/CE
2
LOW to High-Z
[6]
CE
1
LOW/CE
2
HIGH to Power-Up
[7]
CE
1
HIGH/CE
2
LOW to
Byte Enable to Low-Z
Byte Disable to High-Z
Power-Down
[7]
Byte Enable to Data Valid
Description
[4]
-8
Min.
1
8
8
3
8
5
1
5
3
5
0
8
5
1
5
8
6
10
7
1
0
3
1
3
Max.
Min.
1
10
-10
Max.
Min.
1
12
10
3
10
5
1
5
3
5
0
10
5
1
5
12
8
-12
Max.
Unit
ms
ns
12
12
6
6
6
12
6
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
DD
(3.0V). As soon as 1ms (T
power
) after reaching the
minimum operating V
DD
, normal SRAM operation can begin including reduction in V
DD
to the data retention (V
CCDR
, 2.0V) voltage.
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and specified transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise.
5. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. t
power
time has to be provided initially before a Read/Write operation
is started.
6. t
HZOE
, t
HZCE
, t
HZWE
, t
HZBE
and t
LZOE
, t
LZCE
, t
\LZWE
, t
LZBE
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured
卤200
mV from
steady-state voltage.
7. These parameters are guaranteed by design and are not tested.
8. The internal Write time of the memory is defined by the overlap of CE
1
LOW (CE
2
HIGH) and WE LOW. Chip enables must be active and WE and byte enables must
be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the
leading edge of the signal that terminates the Write.
9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
Document #: 38-05256 Rev. *D
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